VPA 架構以 FPGA 模擬驗證技術

無人機飛行系統國產自主關鍵技術開發計畫

"VPA（Visual Processing Accelerator）架構以 FPGA 模擬驗證技術"是一套針對視覺處理加速器(VPA)之系統級驗證方法，透過 FPGA 平台模擬其架構行為與資料流。該技術可於晶片實作前驗證模型推論流程與系統整合，降低開發風險，並支援後續晶片與系統設計之可移轉應用。

The FPGA-Based Emulation and Verification Technology for VPA (Visual Processing Accelerator) Architecture is a system-level validation approach for visual processing accelerators. By emulating VPA architectural behavior and dataflow on FPGA platforms, this technology enables early verification of inference pipelines and system integration, reducing development risk and supporting technology transfer to future chip and system designs.