低功耗運算加速晶片技術

智慧仿生多足機器人技術研發及場域應用計畫

Core Architecture: Low-power FPGA acceleration module based on AMD/Xilinx Zynq UltraScale+.

I/O Capability: Supports 4+ multi-channel CMOS sensor inputs with format interfacing.

Synchronization: High-precision timing synchronization with a computing error of < 3ms via hardware acceleration logic.

雛型實驗室階段

達成多通道影像融合、低同步誤差(<3ms)、低功耗<5W FPGA晶片驗證平台，將來導入微型化晶片並嵌入AI識別功能，有助機器狗與機器人微型化設計，大幅降低功耗與感知反應處理時間

晶片設計開發與驗證

Xilinx MPSOC xczu19eg-ffvc1760-2-i  FPGA platform

電力、電子、資訊相關基礎

本技術已完成基於 AMD/Xilinx Zynq UltraScale+ 異質架構為核心之低功耗 FPGA 運算加速模組。該平台整合了多通道影像通訊技術，可同時支援 4 組以上 CMOS 感測器之影像輸入與感測資料格式對接。透過優化之硬體加速邏輯，系統實現了高精度的多感測器時序同步，運算時序誤差控制在 3ms 以內。目前已成功建構為感知運算系統之快速驗證平台，具備高效能、低延遲與高擴充性之優勢。

This technology features a low-power FPGA acceleration module built on the AMD/Xilinx Zynq UltraScale+ heterogeneous architecture. By integrating multi-channel image communication technology, the platform supports simultaneous inputs from four or more CMOS sensors and facilitates seamless sensor data format interfacing. Leveraging optimized hardware acceleration logic, the system achieves high-precision multi-sensor timing synchronization, maintaining computing timing errors within 3ms. This platform has been successfully established as a rapid verification environment for perception computing systems, offering the advantages of high performance, low latency, and high scalability.